Static timing analysis

Results: 58



#Item
41Electronic circuit simulation / SPICE / Synopsys / Power network design / Logic simulation / Verilog / Static timing analysis / Reliability engineering / Silvaco / Electronic engineering / Digital electronics / Electronic design automation

Datasheet CustomSim High-performance, high-capacity FastSPICE simulation Overview

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Source URL: www.synopsys.com

Language: English - Date: 2015-02-18 14:15:51
42Signoff / Synopsys / Static timing analysis / Signal integrity / Electronic circuit simulation / Delay calculation / Logic simulation / Parasitic extraction / SPICE / Electronic engineering / Electronic design automation / Digital electronics

Datasheet NanoTime Transistor-level Static Timing Analysis Solution for Custom Designs Overview

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Source URL: www.synopsys.com

Language: English - Date: 2015-02-27 00:06:11
43Electronic design / Integrated circuits / Digital electronics / Signal integrity / Static timing analysis / System on a chip / Parasitic extraction / Electronic circuit / MOS Technology SID / Electronic engineering / Electronics / Electronic design automation

PROJECT PROFILE 2A704: Robust design for efficient use of nanometre technologies (ROBIN) EDA FOR SOC DESIGN AND DFM

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Source URL: www.catrene.org

Language: English - Date: 2009-03-25 10:35:46
44Integrated circuits / Formal methods / Signoff / Dynamic random-access memory / Static timing analysis / Electronic design automation / Synopsys / SPICE / System on a chip / Electronic engineering / Electronic design / Electronics

White Paper The Benefits of Static Timing Analysis Based Memory Characterization September 2012

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Source URL: www.synopsys.com

Language: English - Date: 2014-11-07 14:32:46
45Static timing analysis / Electronic design automation / Signoff / Timing closure

White Paper PrimeTime® Mode Merging Reducing Analysis Cost for Multimode Designs August 2013

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Source URL: www.synopsys.com

Language: English - Date: 2014-11-07 14:33:39
46Timing closure / Physical design / Design closure / Integrated circuit design / Static timing analysis / ECO / Synopsys / Signal integrity / Design rule checking / Electronic engineering / Electronic design automation / Signoff

White Paper Signoff-Driven Timing Closure ECO in the Synopsys Galaxy Platform February 2014

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Source URL: www.synopsys.com

Language: English - Date: 2014-11-07 14:32:38
47Capacitance / Coupling / Delay calculation / Static timing analysis / Physics / Mechanical engineering / Electricity

Timing analysis comprehending mask misalignment due to Double Patterning Arvind NV, Ajoy Mandal Texas Instruments India

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Source URL: tauworkshop.com

Language: English - Date: 2014-04-28 21:47:10
48Computer memory / Formal methods / Electronic design / Altos Design Automation / Static timing analysis / Integrated circuit design / Signoff / CPU cache / Random-access memory / Electronic engineering / Electronic design automation / Digital electronics

Technical White Paper High-Performance, High-Precision Memory Characterization Federico Politi, Altos Design Automation, Inc. High-Performance, High-Precision Memory Characterization

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Source URL: www.altos-da.com

Language: English - Date: 2009-07-14 19:10:38
49Formal methods / Altos Design Automation / Statistical static timing analysis / Static timing analysis / Timing closure / Standard cell / SPICE / Process variation / Synopsys / Electronic engineering / Electronic design automation / Software

Variety MX Improve your view… Variety MX expands on Altos’ Liberate MX macro block characterization capabilities to include statistical timing models that account for both global (systematic) and local (random) proce

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Source URL: www.altos-da.com

Language: English - Date: 2009-12-15 20:45:08
50Altos Design Automation / Mentor Graphics / Synopsys / Static timing analysis / Verilog / Electronic circuit simulation / SPICE / Electric / Cadence Design Systems / Electronic engineering / Electronic design automation / Software

Liberate LV Improve your view… Liberate LV provides a collection of utilities for validating libraries including functional equivalence checking, data consistency checking, revision analysis and correlation with variou

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Source URL: www.altos-da.com

Language: English - Date: 2009-07-14 19:09:50
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